According to the trend for the development of integrated circuits, the integration of integrated circuits is increased as large as possible. Many techniques to shrink the dimension of devices are implemented to increase the density of the devices on a silicon wafer.
To reduce the dimension of devices is accompanied by many problems, such as short-channel effect. Besides, the contact resistance of the devices is increased. After the metallization process of the devices, the contact resistance between an active region and a metallic contact of a large-size device is lower than that of a small-size device. Simultaneously, the performance of the small-size devices will be degraded. Thus, a method to manufacture a gate, which is made of metal material, is proposed to reduce the contact resistance between the gate and the substrate and also the gate sheet resistance. In the following descriptions, a method for fabricating a metal gate is described.
Referring to FIG. 1, a substrate 100 is used to be a basis for integrated circuits. A gate oxide layer 110 is deposited on the substrate 100 and a polysilicon layer 120 is then deposited on the gate oxide layer 110. A barrier layer 130 and a metal layer 140 are sequentially deposited. At last, a silicon nitride layer 150 covers the metal layer 140.
As the metal layer 140 will react on the polysilicon layer 120 to form a silicide layer between the metal layer 140 and the polysilicon layer 120, a barrier layer 130 is used to prevent from the formation of the silicide layer. Besides, an ohmic contact is formed between the metal layer 140 and the polysilicon layer 120. Another reason for using the barrier layer is to prevent metal ions from diffusing into the gate oxide layer 110 during the following process for integrated circuits. If the gate oxide layer 110 is degraded, the devices could not be operated. As a lower resistance of the metal gate, a current can be easily transfer through the metal gate.
In memory devices, source/drain regions must be connect to metal contacts. The silicon nitride layer 150 on the metal layer 140 is served as a etching protective layer for a self-aligned contact process of the source/drain regions to protect the metal layer 140. The silicon nitride layer 150 is not needed for the process of all kinds of devices, for example, the process for fabricating logic circuits do not comprise the self-aligned contact stage. So, the silicon nitride layer 150 could be optionally deposited.
Referring to FIG. 2, the layers on the substrate are etched to define the metal gate of integrated circuits. A resistance pattern (not shown) is defined on the silicon nitride layer 150 by using lithography technology. Afterwards, the silicon nitride layer 150, the metal layer 140, the barrier layer 130, the polysilicon layer 120 and the gate oxide layer 110 are anisotropically etched by using a plasma etching process.
Referring to FIG. 3, after the definition of the metal gate, a silicon nitride layer is deposited to cover the surface of the gate and the substrate 100. A dry etching is performed to etch the silicon nitride layer and silicon nitride spacers are formed to on the sidewalls of the gate to serve as an insulating layer.
Metal gates exhibit a low sheet resistance. Nevertheless, oxidation or cleaning process is needed during the process, as is shown in FIG. 2. The process for forming lightly doped drains or a process, which is implemented in an oxygen ambient, will cause the devices failure. As the volume of the layers is changed after an oxidation process, a stress is induced in the metal gate so that the layers on the substrate peel off.
An issue about the metal gate is that the metal gate is etched or degraded by an acid solution or a base solution during cleaning processes. Thus, the metal gate must be protected so that a device with the metal gate has a high reliability.